1. Field of the Invention
The present invention relates to an information processing apparatus having a general-purpose processor, a main memory, a graphics processor, a graphics memory, etc., to draw graphics such as polygons and sprites.
2. Description of the Prior Art
FIG. 1 shows an information processing apparatus according to a prior art, for drawing graphics.
The apparatus has a processor unit 1, a graphics processor unit (GPU) 3, a main memory 5, and a main bus 7 that connects them to one another. The GPU 3 is connected to a graphics memory 9 through a graphics bus 11.
The GPU 3 has a pre-process part 13 and a main process part 15. The main process part 15 employs digital differential analyzers (DDAs), to read texture information from the graphics memory 9, carry out rendering on pixels, and write a resultant image in a frame buffer in the graphics memory 9. The pre-process part 13 calculates parameters such as initial and differential values for the DDAs of the main process part 15.
The processor unit 1 has a processor core 17, which reads a program from the main memory 5 and executes the same. According to the program, the processor core 17 generates GPU command information such as the two-dimensional coordinates and color information of each vertex of a polygon to draw. The processor core 17 employs a geometry translation processor 19 for translating three-dimensional coordinates into two-dimensional coordinates. According to the program, the processor unit 1 adds, to the GPU command information, an identification command indicating the kind of the polygon to draw. According to the GPU command information and additional information, the processor unit 1 generates a GPU command and sends it to the GPU 3 through the main bus 7, so that the GPU 3 may draw the polygon. The GPU command may be sent through a dedicated bus instead of the main bus 7. A speed of sending the GPU command of the processor unit 1 may not be equal to a speed of drawing the polygon of the GPU 3. In this case, the main memory 5 buffers the GPU command, to absorb the speed difference.
According to the GPU command from the processor unit 1, the GPU 3 draws the polygon. FIG. 2 shows data of vertexes of a triangle as an example of the polygon to draw. The triangle has three vertexes whose coordinates are sent with a triangle drawing instruction from the processor unit 1 to the GPU 3. In FIG. 2, a variable having a prefix xe2x80x9cxxe2x80x9d represents an x-coordinate, one having a prefix xe2x80x9cyxe2x80x9d a y-coordinate, one having a prefix xe2x80x9czxe2x80x9d a z-coordinate, one having a prefix xe2x80x9crxe2x80x9d red color information, one having a prefix xe2x80x9cgxe2x80x9d green color information, one having a prefix xe2x80x9cbxe2x80x9d blue color information, one having a prefix xe2x80x9caxe2x80x9d an a-coordinate, one having a prefix xe2x80x9cuxe2x80x9d a u-coordinate, and one having a prefix xe2x80x9cvxe2x80x9d a v-coordinate of a given vertex.
The pre-process part 13 carries out calculations shown in FIG. 3 and sends parameters shown in FIG. 4 to the main process part 15. FIG. 5 shows a standard arrangement of the pre-process part 13 for carrying out the calculations of FIG. 3.
The main process part 15 sets the received parameters in the DDAs, reads texture information from the graphics memory 9, and draws the polygon with the use of the DDAs.
FIG. 6 shows an example of the main process part 15 having the DDAs. The DDAs include DDA-u, DDA-v, and DDA-q for determining texture coordinates to read, DDA-r, DDA-g, DDA-b and DDA-a for determining colors to draw, a DDA-z for determining a z-buffer, and DDA-edge-1, DDA-edge-2, and DDA-edge-3 for determining coordinates to draw.
A method of drawing graphics will be explained. According to determined coordinates, a z-value is read out of the frame buffer in the graphics memory 9. The z-value is compared with a corresponding one in the determined coordinates. If the read z-value is closer to a view point than the determined one, the point in question is drawn. If not so, the point is not drawn, and the next point is processed. Drawing the point is carried out by overwriting the z-value and color information for the point in the frame buffer.
The color information in the frame buffer is scanned and displayed on a display.
FIG. 7 shows an information processing apparatus according to another prior art, employing two GPUs 3a and 3b to improve graphics drawing performance.
The prior art fabricates the GPUs and a graphics memory on separate chips, to restrict a band width in the graphics bus 11 and hinder high-speed I/O operations with respect to the GPUs. The band width is calculated by multiplying the operation frequency of the bus by bit width. The prior art is incapable of letting the apparatus demonstrate high performance even if the GPUs can operate at high speed.
The apparatus of FIG. 7 having the multiple GPUs may be inexpensive but has only one graphics memory. This and the band width in the graphics bus result in not fully utilizing the capacity of the GPUs. It is possible to provide a graphics memory for each of the GPUs. This, however, increases the quantities of wiring and graphics DRAMs, to increase the cost.
An object of the present invention is to provide an information processing apparatus having a GPU and a graphics memory that are formed in a multi-processor system, to realize high graphics drawing performance.
Another object of the present invention is to provide an information processing apparatus having a plurality of sub-systems in a cascade fashion, to easily modify the design of the whole system in order to improve the performance by increasing the number of the sub-systems available.
In order to solve the above-mentioned objects, in accordance with the present invention, an information processing apparatus comprising a plurality of graphic sub-systems connected in series to each other, each of said graphic sub-systems comprises: a processing unit for executing a graphical program; a main memory connected to said processing unit for storing said graphical program and graphical data for use in executing said graphical program; a graphic processor unit connected to said processing unit for performing calculation required to obtain internal video data with z-values as prepared by said processing unit in accordance with said graphical program, wherein said graphic processor unit is provided with a pair of frame buffer areas and a pair of z buffer areas are defined for performing a double buffering technique; and a graphic memory connected to said graphic processor; a selector circuit connected to said graphic processor for receiving said internal video data with z-values and external video data with z-values and outputting said combinational video data with z-values by comparing the z-values of said internal video data and said external video data.
In a preferred embodiment, the information processing apparatus further comprises a controller connected to an external device and connected to said graphic sub-systems through a common bus for receiving command data from an external device and broadcasting said command data to said graphic sub-systems respectively through said common bus.
In a further preferred embodiment, said external device is a Joystick for playing a video game and said command data is generated in response to manipulation of said Joystick by a player.
In a further preferred embodiment, said external video data further includes an xcex1-value, and said selector circuit is capable of functioning as a multiplexer and connected to said graphic processors of said graphic sub-systems for receiving said internal video data and said external video data and outputting said combinational video data by comparing the z-values of said internal video data and said external video data and referring to said xcex1-value.
In accordance with another aspect of the present invention, an information processing apparatus comprising a plurality of graphic sub-systems, each of which comprises: a processing unit for executing a graphical program; a main memory connected to said processing unit for storing said graphical program and graphical data for use in executing said graphical program; a graphic processor unit connected to said processing unit for performing calculation required to obtain internal video data with z-values as prepared by said processing unit in accordance with said graphical program, wherein said graphic processor unit is provided with a pair of frame buffer areas and a pair of z buffer areas are defined for performing a double buffering technique; and a graphic memory connected to said graphic processor, wherein said information processing apparatus further comprising a controller connected to said graphic sub-systems through a common bus and a selector circuit connected to said graphic processors of said graphic sub-systems for receiving said internal video data and outputting combinational video data by comparing the z-values of said internal video data of the respective graphic sub-systems.
In a preferred embodiment, said graphic program includes first and second modules, the first module consisting of routines for mathematical calculations required to determine motion data as interpreted in the three dimensional motion space and the second module consisting of routines for mathematical calculations required to a two-to-three dimensional conversion.
In a further preferred embodiment, the first module consisting of routines for mathematical calculations required to determine motion data a macro objects as interpreted in the three dimensional motion space and the second module consisting of routines for mathematical calculations required to divide said macro object into a plurality of micro objects.
In a further preferred embodiment, the second module consisting of routines for mathematical calculations required for light source handling.
In a further preferred embodiment, the first module is redundantly executed in each of said graphic sub-systems while the second module is differently executed in each of said graphic sub-systems in accordance with at least one of objects assigned to said each of said graphic sub-systems.
In a further preferred embodiment, said at least one of objects is a character of a video game.
In a further preferred embodiment, said external video data further includes an xcex1-value, and said selector circuit is capable of functioning as a multiplexer and connected to said graphic processors of said graphic sub-systems for receiving said internal video data and said external video data and outputting said combinational video data by comparing the z-values of said internal video data and said external video data and referring to said xcex1-value.
In accordance with another aspect of the present invention, an information processing apparatus comprising a plurality of graphic sub-systems connected in series to each other, each of said graphic sub-systems comprises: a processing unit for executing a graphical program; a main memory connected to said processing unit for storing said graphical program and graphical data for use in executing said graphical program; a graphic processor unit connected to said processing unit for performing calculation required to obtain internal video data with z-values as prepared by said processing unit in accordance with said graphical program; a graphic memory connected to said graphic processor; an input port for receiving external video data with z-values; an output port for outputting combinational video data of said internal video data and said external video data; and a selector circuit connected to said graphic processor for receiving said internal video data and said external video data and outputting said combinational video data by comparing the z-values of said internal video data and said external video data.
In a preferred embodiment, the information processing apparatus further comprises a controller connected to an external device and connected to said graphic sub-systems through a common bus for receiving command data from an external device and broadcasting said command data to said graphic sub-systems respectively through said common bus.
In a further preferred embodiment, said external device is a joystick for playing a video game and said command data is generated in response to manipulation of said joystick by a player.
In a further preferred embodiment, said two-dimensional view to be actually displayed on the monitor is a bird""s-eye view of the geographical data as prepared by the graphical program.
In a further preferred embodiment, one of said sub-systems is prepared responsible for handling two-dimensional view of one or more motion character while another of said sub-systems is prepared responsible for handling two-dimensional view of the background view.
In a further preferred embodiment, said external video data further includes an xcex1-value, and said selector circuit is capable of functioning as a multiplexer and connected to said graphic processors of said graphic sub-systems for receiving said internal video data and said external video data and outputting said combinational video data by comparing the z-values of said internal video data and said external video data and referring to said xcex1-value.
In accordance with another aspect of the present invention, an information processing apparatus comprising a plurality of graphic sub-systems connected in series to each other, each of said graphic sub-systems comprises: a processing unit for executing a graphical program; a main memory connected to said processing unit for storing said graphical program; a graphic processor unit connected to said processing unit for performing calculation required to obtain internal video data with z-values and an xcex1-value as prepared by said processing unit in accordance with said graphical program; a graphic memory connected to said graphic processor; an input port for receiving external video data with z-values; an output port for outputting combinational video data of said internal video data and said external video data; and a selector-multiplier circuit connected to said graphic processor for receiving said internal video data and said external video data and outputting said combinational video data in accordance with xcex1 value by comparing the z-values of said internal video data and said external video data.
In a preferred embodiment, the information processing apparatus further comprises a controller connected to an external device and connected to said graphic sub-systems through a common bus for receiving command data from an external device and broadcasting said command data to said graphic sub-systems respectively.
In a further preferred embodiment, said external video data further includes an xcex1-value, and said selector circuit is capable of functioning as a multiplexer and connected to said graphic processors of said graphic sub-systems for receiving said internal video data and said external video data and outputting said combinational video data by comparing the z-values of said internal video data and said external video data and referring to said xcex1-value.